(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to form a relaxed semiconductor buffer layer prepared for subsequent accommodation of an overlying semiconductor layer featuring a tensile strain.
(2) Description of Prior Art
The ability to form devices such as a metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor layer comprised with tensile strain has allowed the performance of the MOSFET to be increased via enhanced mobility of carriers in the strained semiconductor layer channel region. This can be achieved for several applications such as a strained silicon layer on an underlying relaxed silicon-germanium layer, or an underlying relaxed InGaAs layer on a GaAs substrate, accommodating an overlying strained layer. Methods of forming tensile strained layers such as a silicon layer as an example, include forming the silicon layer on an underlying relaxed layer such as a silicon-germanium layer. The relaxed silicon-germanium layer located on an underlying silicon substrate has been called a silicon-germanium virtual substrate. The growth of a relaxed semiconductor layer such as silicon-germanium can be challenging since it encompasses controlled nucleation, propagation, and interaction of misfit dislocations that terminate with threading arms that extend to the surface and then can be replicated in subsequently grown layers such as the overlying strained silicon layer which will be employed for accommodation of a subsequent device. The defects in the strained silicon layer propagated from the misfit dislocations in the underlying relaxed silicon-germanium layer, can deleterious influence MOSFET leakage and yield.
The crystalline quality of the relaxed silicon-germanium layer can be improved by growing a compositionally graded, thick silicon-germanium layer at a thickness greater than a micrometer. The compositionally graded relaxed layer can be achieved via increasing the germanium content from the bottom to the top surface of the compositionally graded silicon-germanium layer, with this sequence resulting in increased lattice mismatch at the top surface of the graded semiconductor alloy layer. Another approach which will be featured in the present invention is creation of a compositionally graded silicon-germanium layer, however featuring decreasing germanium content from the bottom to the top surface of the compositionally graded semiconductor alloy layer. This approach uses the highest lattice mismatch, as well as the maximum dislocation formation, near the underlying semiconductor surface resulting in yield and process benefits when compared to counterpart compositionally graded semiconductor alloy layers. Prior art such as Chu et al in U.S. Pat. No. 6,649,492 B1, Fitzgerald in U.S. Pat. No. 6,649,322 B2, and Cheng et al in U.S. Pat. No. 6,515,335, have described methods of varying germanium content in a silicon-germanium layer as well as forming a graded silicon-germanium layer to spread lattice mismatch minimizing dislocation propagation. The above prior art however do not describe the unique sequence described in the present invention for formation of a semiconductor alloy layer featuring a relaxed, low defect layer needed for accommodation of an overlying strained semiconductor layer, that is a process sequence allowing the largest lattice mismatch to occur at the semiconductor substrate-semiconductor alloy interface.